1. Field of Invention
The present invention relates to a method of manufacturing an inter-metal dielectric layer. More particularly, the present invention relates to a method of manufacturing an inter-metal layer which can decrease the resistor-capacitor time delay (RC time delay) in a device.
2. Description of Related Art
In the process for manufacturing an ultra large-scale integrated circuit, more than a hundred thousand transistors are located on a silicon substrate within an area of about 1-2 square centimeters. Additionally, in order to increase the integration of the integrated circuits (ICs), the density of wires used to electrically couple the transistors to each other or the other devices to each other is increased. Therefore, in accord with the increased interconnect manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two metal layers. In particular, a number of function-complicated products, such as microprocessors, even require 4 or 5 metal layers to complete the internal connections. Generally, an inter-metal dielectric (IMD) layer is used to electrically isolate two adjacent metal layers from each other. Moreover, a conductive layer used to electrically connect the two adjacent metal layers is called a via plug in the semiconductor industry.
However, due to the increasingly high integration of ICs, the distance between the adjacent wires is decreased. If the dielectric constant of the IMD layer used an electrically isolating material between the wires can not be efficiently decreased, the rate of data transmission between the devices is decreased due to the increasing of the RC time delay. Hence, the ability of the devices is limited.